Some of the brightest minds in the CPU industry – including Intel, AMD, Qualcomm, Arm, TSMC and Samsung – are coming together to define a new standard for chiplet-based processor designs. The new standard, called Universal Chiplet Interconnect Express (UCIe for short), aims to define an open, interoperable standard for combining multiple silicon dies (or chiplets) into a single package.
Intel, AMD, and others are already developing or selling some form of chiplet-based processors — most of AMD’s Ryzen CPUs use chiplets, and Intel’s forthcoming Sapphire Rapids Xeon processors will too. However, these chips all use different connections to allow communication between chiplets. The UCIe standard, if successful, will replace these with a single standard, theoretically making it much easier for smaller companies to take advantage of chiplet-based designs, or for one company to integrate another company’s silicon into its own products .
Chiplet-based designs are beneficial when manufacturing large chips on state-of-the-art manufacturing nodes, in part because they reduce the amount of silicon manufacturers have to throw away. When a manufacturing defect affects a CPU core, throwing away (or binning) a single 8-core chiplet is a lot cheaper than throwing away a giant 16- or 32-core processor chip. Chiplet designs also allow you to combine chips and manufacturing processes. For example, you could use an older, cheaper process for your chipset and a newer, state-of-the-art process for your processor cores and cache. Or you could put an AMD GPU in the same package as an Intel CPU.
As AnandTech reports, the UCIe standard will cover the physical and protocol layers of chiplet design. The standard will define how the chiplets must be connected together and the protocol to facilitate communication between chiplets. However, chip designers are free to package these chiplets in any way they see fit, allowing the chiplets to communicate with each other directly through the package substrate, or using some sort of silicon-based bridge or other intermediary.
To accommodate these different physical packaging options, version 1.0 of UCIe defines two different performance levels. The “standard” package requires 16 data lanes and up to 25mm of space between chiplets, while the “enhanced” package uses 64 data lanes and only allows 2mm of space.
The protocols underlying UCIe are PCI Express and related Compute Express Link (CXL) standards, which are both mature and familiar to chipmakers. But companies that have already developed more advanced or specific protocols for chiplet-to-chiplet communication, such as AMD and its Infinity Fabric, can use those protocols while remaining UCIe compliant. Developed primarily by Intel, UCIe was then donated to the broader UCIe group to serve as the basis for the new standard. But the group’s member companies “will start working together on the next generation of UCIe technology from the end of this year”.
If you want more technical details on the UCIe standard, you can find the white paper here.
Listing image by AMD